CPU Microarchitecture

A deep dive into CPU microarchitecture on Intel Granite Rapids - cache coherence and MESI, hardware/software prefetching, and IOMMU-based device isolation
  1. Why Innocent Shared Updates Stop Scaling: Cache Coherence on a Multi-Socket Server
    How a one-line counter update turns into cross-core and cross-socket communication. Microbenchmarks on a dual-socket server separate local atomic cost, ownership handoffs, true sharing, and false sharing, and map each to a fix.